1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a column selection circuit which is effective when used with a video memory which stores image data.
2. Description of the Prior Art
Semiconductor memory devices have plural bit data input/output (I/O) terminals, and read and write data in block units (hereinafter referred to as "words") equal to the bit width of the data in the data I/O terminals. The wider the bit width of the data word, the greater the number of bits which can be read or written in a single access operation, thereby enabling high speed data access.
The construction of a conventional semiconductor memory device is shown in FIG. 7. The data storage section, which is comprised of memory cells for storing the data, is arrayed in block units as shown by memory cell blocks 2a and 2b. A single memory plane 1-1 is formed by the two memory cell blocks 2a and 2b, which share a column decoder 4. The complete data storage unit is formed by providing n memory planes (1-1 to 1-n).
Each memory plane 1-1 to 1-n comprises memory cell blocks 2a and 2b, row decoders 5a and 5b, column decoder 4, and column selection gates 3a and 3b. The data word in each memory cell block is selectively connected to the data buses 6-1, 6-2, 6-3, 6-4, . . . 6-(2n-1), 6-(2n) according to the address signal provided by an address signal input means (not shown). The block selection gates 7-1, 7-2, 7-3, 7-4, . . . 7-(2n-1), 7-(2n) select data from a word on each memory cell block data bus 6-1, 6-2, 6-3, 6-4, . . . 6-(2n-1), 6-(2n), and outputs the data to the data I/O bus 9. The block selection signals 8-1, 8-2, 8-3, 8-4, . . . 8-(2n-1), 8(2n) are generated so that one of the signals is selected according to the address signal supplied by the address signal input means.
The write circuit 10 outputs the data supplied from the data I/O terminal 12 in the write operation to the data I/O bus 9. The read circuit 11 outputs the data or to the data I/O bus 9 to the data I/O terminal 12 in the read operation.
In this device, the bit width of the each of buses 6-1, 6-2, 6-3, 6-4, . . . 6-(2n-1), 6-(2n) and the data I/O bus 9 is the bit width of the data word, and is equal to the bit width of the data I/O terminal 12.
FIG. 8 is a schematic diagram of a column selector wherein the data bus 6 has a bit width equal to 4 bits. The column selection gate 3 has a plurality of switching transistors T0 . . . Tm which are connected to bit line outputs B0 . . . Bm in the memory cell block 2, respectively. The first four switching transistors T0 . . . T3, which are in group 3-1, are connected to data bus lines D0 . . . D3, respectively. Similarly, the second four switching transistors T4 . . . T7, which are in group 3-2, are connected to data bus lines D0 . . . D3. Likewise, four switching transistors in a group are each connected to data bus lines D0 . . . D3. Furthermore, the gate electrodes of the first four switching transistors T0 . . . T3 in group 3-1 are commonly connected to output C0 of column decoder 4. Similarly, the gate electrodes of the second four switching transistors T4 . . . T7 in group 3-2 are commonly connected to output C1 of column decoder 4. Likewise, the gate electrodes of four switching transistors in a group are commonly connected to one output of the column decoder 4.
The column decoder 4 drives one of the outputs C0 . . . Cn to designate one group according to the address signal supplied by the address signal input means. The four switching transistors in the designated group 3-1, 3-2, 3-3, or 3-n are driven by the output from the column decoder 4, so that selected 4-bit data are produced from the memory cell block 2 through corresponding four outputs of bit line outputs B0 . . . Bm, and are further applied to four lines in the data bus 6. Thus, each memory cell block is accessed in units equal to the bit width of the data bus 6, and the bit position of the data bus 6 to which each bit line output B0 . . . Bm corresponds is fixed. In other words, according to the prior art semiconductor memory device shown in FIG. 8, it is possible to access the previously grouped four consecutive outputs B0 . . . B3 simultaneously, but it is not possible to access simultaneously four consecutive outputs in other combinations, such as B1 . . . B4, B2 . . . B5 or B3 . . . B6.
FIG. 9 is a circuit diagram of the block selection gate 7. The block selection gates 7-1 to 7-(2n) are driven by the block selection signals 8-1 to 8-(2n), respectively. Each block selection gate, e.g. gate 7-1, comprises four switching transistors inserted in four lines D0 . . . D3, respectively. The four lines D0 . . . D3 are in turn connected to four lines in the data I/O bus 9. By one of the block selection signals 8-1 to 8(2n) being driven according to the address signal provided by the address signal input means, one of the data buses 6-1 . . . 6-(2n) is selected and connected to the data I/O bus. The lines in data I/O bus 6 are connected respectively to the lines in data I/O bus 9 at the block selection gate 7.
As thus described with respect to a conventional semiconductor memory device above, the bit width of a single word, which is the bit width of the data I/O terminals, is increased to enable high speed data access, and the memory area is accessed by specifying the address position in word units. When a semiconductor memory of this construction is used as a computer data storage device no problems are encountered because the memory is accessed in units with each unit having a predetermined bit width, but the following problems occur when this memory device is used as a video memory for image data storing.
According to the semiconductor memory device described above, it is not possible to simultaneously access the four consecutive bits of data which are in a combination other than the previously grouped combination. This disadvantage is further explained below.
FIG. 10 illustrates data access in the display image area of a semiconductor memory device used for video memory and storing image data to be displayed as a graphic image on screen. The memory is accessed in 4 bit word units at each address, and the data at the set positions corresponds to each bit D0 . . . D3 at the data I/O terminal. It is desirable to use a large data I/O terminal bit width and to increase the data width which can be accessed in a single video memory access operation in order to achieve high speed image data processing. However, image data accessed for processing is accessed in pixel (bit) units, and the address position specification is in bit units regardless of the bit width of the data word.
Because specifying an address position is only possible in word units equal to the bit width of the data I/O terminal in a conventional semiconductor memory device, the use of such memory devices as a video memory necessitates the use of an external barrel shifter to shift the bit position, or a mask processing circuit to mask the bits not read or written, thus complicating the video memory structure. In addition, the shift operation of the barrel shifter and the masking operation require the memory to be accessed multiple times at the bit width of the data I/O terminal, resulting in a slower processing time.